The present invention relates to solid-state imaging apparatuses capable of special read-out, such as read-out at a desired magnified rate, and more particularly to a solid-state imaging apparatus permitting special read-out capable of reducing the numbers of lead lines and connection electrodes to connect shift gate control gate electrodes to an external circuit.
Recently, development of so-called electronic still cameras, which are electronic imaging apparatuses capable of inputting image data to multi-media systems, is in force. The electronic still camera usually uses a solid-state imaging unit, such as a CCD imaging device, for obtaining images. The image obtained in such a camera is displayed on a liquid crystal panel of like view-finder, and can also be recorded in a recording medium in response to the depression of a trigger by the user. It has been demanded to further improve the image quality and operation control property of the electronic camera. To meet these demands it is indispensable to use a CCD imaging device having a large number of pixels and also that it is desirable to real time confirm image of the same view angle as picked-up image with a view-finder.
By using a high density pixel CCD imaging element, however, although the high quality image is obtainable, the rate of reading out one frame image is reduced, and images which are recognized as motion picture images can not be displayed on the view-finder.
To cope with this problem, Japanese Patent Laid-Open No. 10-136244, for instance, proposes line addition read-out, in which charge of each pixel in a row in an array are added together, or thin-down read-out, in which pixels in columns are thinned down. Such read-out permits high rate frame-by-frame read-out of the image, although image quality is sacrificed. It is thus made possible to cope with the motion picture image display problem.
However, the disclosed line addition or thin-down read-out method(s) is proposed for non-interlace systems, and no specific technique of high rate read-out system has been disclosed for any interlace system.
FIG. 6 shows a construction which is conceivable in the case where the interlace system is applied to the usual inter-line type CCD imaging device. This example is of four-phase drive type with a least recurrence unit of two pixels. For the sake of the brevity, 16 pixels are shown as a set. These sets of pixels are arranged successively one after another in the vertical direction of vertical transfer path. In the Figure, reference numerals 1 to 16 within rectangles each designate each pixel 1. A vertical transfer path 2 has two groups a and b of vertical transfer electrodes 1a, 1b to 16a, 16b. Two like sequence transfer electrodes in the two electrode groups are provided for each of the pixels in each set. Each pixel 1 is connected via a shift gate 3 to each transfer channel in the vertical transfer path 2 corresponding to each of the transfer electrodes 1a to 16a in the electrode group a. The vertical transfer electrodes are connected to corresponding ones of four shift pulse application lead lines 4, via which 4-phase shift pulses out of phase by ¼ cycle with one another are applied. The 4-phase transfer pulses are successively applied to the transfer electrodes, which are grouped in groups each of four transfer electrodes, whereby the charge read out via the shift gates to the vertical transfer path 2 are transferred in one direction. In FIG. 6, reference numeral 5 designates connection electrodes for connecting the lead lines 4 to an external circuit.
Of the transfer electrodes in the vertical transfer path 2, those 1b to 16b in the electrode group b merely serve for the charge transfer. The transfer electrodes 1a to 16a in the electrode group a, on the other hand, do not only serve for the charge transfer, but also serve as common gate pulse application electrodes for turning on the shift gates 3. Thus, while a charge transfer operation is caused by application of a normal shift pulse, when a voltage in excess of a predetermined voltage as a predetermined timing is selectively applied to predetermined transfer electrodes in the electrode group a, the shift gates 3 corresponding to the selected transfer electrodes are turned on to cause the pixel charge read-out to the vertical transfer path 2.
In the case of the 4-phase drive, four transfer channels of the vertical transfer path corresponding to 4-frame transfer electrode unit, for instance, the transfer electrodes 1a, 1b and 2a, 2b, constitutes a unit, so that only charge for only one pixel can be read out. Thus, the pixels that are involved in the shift along the vertical transfer path 2 correspond in number to one half the intrinsic number of vertically arranged pixels. This corresponds to the scanning in the interlace system.
In the CCD imaging device of the above interlace system, a construction as shown in FIG. 7 is conceivable when a high rate (or multiple rate) read out system or like special drive system is to be applied. In this example, the transfer electrodes 1b to 16b in the electrode group b in the vertical transfer path 2 perfectly have only bearing on the charge transfer, and like the 4-phase drive interlace system CCD imaging device shown in FIG. 6 they are connected commonly for every 4-frame transfer electrode unit. The transfer electrodes 1a to 16a in the electrode group a, on the other hand, are for special driving, have to let them also function as shift gate electrodes. The gate pulse should be independently applied to the gate electrode. Thus, it is necessary to provide independent gate pulse application lead lines to all the transfer electrodes 1a to 16a in the electrode group a. However, since in this case a 16-pixel unit recurrence system is adopted, 16 lead lines 4A are provided for independent gate pulse application to the transfer electrodes. While two lead lines are basically provided for the transfer electrodes in the electrode group a, 14 lead lines are newly provided. In addition, two lead lines 4B are provided for the transfer electrodes in the electrode group b. Thus, the total number of lead lines is 18. In FIG. 7, reference numeral 6 designates connection electrodes for connecting the independent gate pulse application lead lines 4A to an external circuit.
The above construction of the CCD imaging device with a successive arrangement of a plurality of pixel groups, in which independent shift gate pulse application lead lines are provided in correspondence to the individual pixels in each pixel group for high rate read-out by appropriately adding together charge of a desired number of pixels, is also disclosed in, for instance, Japanese Patent Laid-Open No. 10-150601. However, this case and also the construction shown in FIG. 7, have a problem that large numbers of lead lines and external circuit connection electrodes should be provided in connection with the independent gate pulse application via the transfer electrodes in correspondence to the number of pixels in each of the successive pixel groups.